1. Field of the Invention
The present invention relates to digital memories. More specifically, the present invention relates digital memory arrays organized in rows and columns and used in various digital devices.
2. Description of the Related Art
Modern computing devices utilize a variety of kinds of memory devices to store and access information. Several memory device technologies are familiar to those skilled in the art and include the general classes of random access memories (“RAM”) and read only memories (ROM”). These classes further comprise static RAM (“SRAM”), dynamic RAM (“DRAM”), programmable ROM (“PROM”), erasable PROM (“EPROM”), electrically erasable PROM (“EEPROM”), as well as FLASH memory, smaller register files, and other memory types known to those skilled in the art. Most memory devices employ an internal architecture in the form of an array of bit-cells, comprised of plural rows and plural intersecting columns. This architecture is beneficial in allowing random access to the memory, and in minimizing the number of circuit components needed to implement any given memory array size. A memory bit-cell is placed at each intersecting row and column in the array. Activating a bit-cell's row and then reading or writing the state of its column provides access an addressed bit-cell. Some memory devices employ dual, or multiple, ports. When multiple access ports are provided in a memory, the number row and column conductors are increased proportionately to the number of ports implemented. Memory sizes are defined by the row and column architecture. For example, a 1024 row by 1024 column memory array defines a memory device having one megabit of memory bit-cells. The memory bit-cells are often times arranged into logical groups of memory bits, called words. A convention has emerged in the art, where the array row conductors are referred to as word-lines and the memory column conductors referred to as bit-lines.
Memory devices are most commonly implemented as semiconductor integrated circuits, which are built up in multiple layers on a semiconductor die. Such circuits are know to those skilled in the art and are comprised of ion doped semiconductor circuit devices, such as diodes and transistors, formed on a substrate and interconnected with metallic traces. During manufacturing, multiple layers of circuitry are built up upon one another, separated with insulating layers. In memory devices organized in the aforementioned array structure, the word-lines and bit-lines are formed with long metallic or poly traces that are electrically tapped at each array junction, where a memory bit-cell has been formed. During manufacture, transistors are formed by diffusing ions into the undoped substrate. By using masking techniques, the various parts of the active devices are arranged. A first metal layer above the diffused transistor layers is called “Metal-1”. In addition, a contact layer is formed between the transistors and Metal 1 that includes holes in the insulating oxide between Metal-1 and the individual transistors' sources, drains and gates, which allows Metal-1 to connect down to the transistors. However, other semiconductor and passive devices are also used, as are known to those skilled in the art. Due to cost, yield, and performance issue that surround the design and manufacture of memory devices, designers are continually challenged to implement logic and schematic designs in an efficient design realizable in a physical memory device. In fact, the conversion of a schematic memory design to a physical device design is the essential challenge in memory design. For any given memory technology, there are a set of minimum design rules that establish the limits of element size and performance. For example, the width of FET channels, the width and thickness of conductive traces, the minimum spacing between layers and between parallel conductive traces, etc. In an efficient memory design, based on minimum design rules, every layer of the device will be fully populated and tightly arranged for maximum utilization of available semiconductor area.
In a typical memory array device, each memory cell is comprised of some number of semiconductor devices interconnected to form the memory bit-cell. For example, in a static memory, each memory cell is formed with four transistors that are interconnected to implement a bit-latch, which is then coupled to corresponding bit-lines with a pair of transistor pass-gates. Thus, each memory bit-cell is created using six transistors. Of course, other memory technologies use other numbers of transistor and/or passive devices. The nodes of the various transistors are interconnected through the aforementioned Contact layer, which is coupled to a first metallic trace layer, known as “Metal-1”. More metallic trace layers can be added to the integrated circuit, each coupling down to Metal-1 layer. However, it is important to note the significant fact that only the “Metal-1” and “Contact” layers afford direct connection to the semiconductor device nodes. When designers generate memory integrated circuit layouts, the space available on the Contact and Metal-1 layers are at a premium and can be a limiting factor in device size and density. Several design rules known to those skilled in the art limit the degree of integration and miniaturization possible. At some point in the design, the only way to reduce the device size or increase its density is to somehow eliminate some of the circuit components or interconnecting metallic traces and connection nodes.
Another aspect in the design of high-density memory device is the complex nature of the interconnection of the array of bit-cells to the associated addressing, decoding and read/write access circuitry. Generally a large number or word-lines rows and bit-lines columns are routed on the upper metal layers of the integrated circuit die. The intersections of the rows and columns define the access locations for each of the plural bit-cells in the array. In particular, the intersection of one word row and one bit column are used to access a single memory bit-cell to either read the data therein or write new data thereto. In the case of multiple port memory arrays, the number of word row and bit column metallic traces is even greater. In the case of a static memory device, each bit column is actually comprised of two bit-lines, a bit-true and bit-compliment line. The differential voltage between the two being used to determine the memory cell contents during a read operation, as well as forcing the state of the bit-cell in a write operation. Access to a particular bit-cell is addressed by enabling that bit-cell's corresponding word-line and then reading its corresponding bit-line. With a large number of parallel metallic traces running crisscross through the chip, and given that fact that each word-line activation turns on all of the bit-cells in a given row, the magnitude of the capacitive load being driven is significant. In addition to the metal-to-ground and metal-to-metal capacitance that the metallic trace routing defines, there is the node capacitance of all the devices that are coupled to an activated row or column. The capacitance is significant because the current needed to drive the circuit depends on the magnitude of the capacitive load. Current flow, or power consumption, in a capacitive circuit is quantified as the circuit capacitance multiplied by the first derivative of the change in voltage with respect to time. Thus, power consumption in the active state of accessing a memory cell is proportional the number of traces and circuit elements that are being driven over the voltage change of the read or write operation in progress.
The problem of excessive capacitive load in memory array read and write operations has been addressed in a separate patent application made by the inventor of the present invention. Filed in U.S. patent application Ser. No. 10/189,072 to Sheppard, entitled MEMORY DEVICE AND METHOD WITH IMPROVED POWER AND NOISE CHARACTERISTICS, the invention describes a way to use multiple word-lines per row to access a fractional part of each row of bit-cells so that the capacitive load of each access is fractionally reduced. Hereinafter, this technology will be referred to as “Multiple Word Line” technology. The Multiple Word Line technology results in lower power consumption and improved noise characteristics over the prior art. The contents of the Multiple Word Line patent application are hereby incorporated in the present disclosure by reference thereto. The additional word-line traces in the related invention are not objectionable because they are implemented in the upper metal layers and do not generally compromise the designer's ability to tightly integrate and miniaturize the integrated circuit design.
Notwithstanding the improvements in the prior art, there still exist practical limits on memory array circuit density in the prior art. The advantages of reduced die size, including lower parts cost and higher manufacturing yields, cannot be realized because of the high number of traces and circuit interconnections required in prior art memory array integrated circuit designs. In the case of multiple port memory devices, this problem is exacerbated. The problem in the prior art is defined and bounded by the need to interconnect plural bit-lines with sense amplifiers, pre-charge circuits, write circuits, and the memory bit-cells themselves, as well as the practical limits on the number of circuits that can be interconnected through the Contact and Metal-1 layers. Thus, there is a need in the art to reduce the number of bit-lines, reduce the number of circuit interconnections and generally reduce the size and complexity of memory array layouts.